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XMEGA A [MANUAL]
8077I–AVR–11/2012
15.7
Register Description
15.7.1 CTRL – Control register
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 5 – PGM: Pattern Generation Mode
Setting this bit enables the pattern generation mode as well as the CWCM mode, and disables the OUTOVEN register
action. This will override the DTI, and the pattern generation reuses the dead-time registers for storing the pattern.
Bit 4 – CWCM: Common Waveform Channel Mode
If this bit is set, the CC channel A waveform output will be used as input for all the dead-time generators. CC channel B,
C, and D waveforms will be ignored.
Bit 3:0 – DTICCxEN: Dead-Time Insertion CCx Enable
Setting these bits enables the dead-time generator for the corresponding CC channel. This will override the timer/counter
waveform outputs.
15.7.2 FDEMASK – Fault Detect Event Mask register
Bit 7:0 – FDEVMASK[7:0]: Fault Detect Event Mask
These bits enable the corresponding event channel as a fault condition input source. Events from all event channels will
be ORed together, allowing multiple sources to be used for fault detection at the same time. When a fault is detected, the
fault detect flag (FDF) is set and the fault detect action (FDACT) will be performed.
15.7.3 FDCTRL - Fault Detection Control register
Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 4 – FDDBD: Fault Detection on Debug Break Detection
By default, when this bit is cleared and fault protection is enabled, and OCD break request is treated as a fault. When this
bit is set, an OCD break request will not trigger a fault condition.
Bit
7
6
5
4
3
2
1
0
+0x00
–
PGM
CWCM
DTICCDEN
DTICCCEN
DTICCBEN
DTICCAEN
Read/Write
R
R/W
Initial Value
0
Bit
7
6
5432
10
+0x02
FDEVMASK[7:0]
Read/Write
R/W
Initial Value
0
0000
00
Bit
7
6
54321
0
+0x03
–
FDDBD
–
FDMODE
FDACT[1:0]
Read/Write
R
R/W
R
R/W
Initial Value
0
00000
0
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